1. Field of Invention
The present invention is related to semiconductor flash memories, and in particular to a twin MONOS flash metal bit array.
2. Description of Related Art
A MONOS EEPROM is comprised of an array of cells that can be independently programmed and read. Metal Oxide Semiconductor (MOS) field effect transistors form the individual memory units of MONOS EEPROM. The Flash MOS transistor includes a source, drain, and floating gate with a control gate connected to a Word Line (WL). Various voltages are applied to the word line and bit lines to program the cell with a binary xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, or to erase the cell.
U.S. Pat. No. 6,248,633 (Ogura et al) is directed toward a twin MONOS cell structure having an ultra short control gate channel with ballistic electron injection into the nitride storage sites and fast low voltage programming. U.S. Pat. No. 6,134,156 (Eitan) is directed toward a method of detecting the content of a selected memory cell including the charging of bit lines and drain lines. An array scheme shown in U.S. Pat. No. 6,011,725 (Eitan) is directed toward a polysilicon word line routed above the control gates of the cells connected to the word line WL, referred to as dual bit NROM cells. U.S. patent application Ser. No. 10/099,030 dated Mar. 15, 2002 is directed toward providing a method of memory cell selection and operation to obtain wide program bandwidth and EEPROM erase capability in a MONOS memory cell.
In FIG. 1A is shown a cross section of a dual bit NROM array of prior art with a word line WL0, bit line diffusions BL0, BL1, BL2 and BL3, and nitride storage sites M0, M1, M2, and M3. The schematic of the dual bit NROM array is shown in FIG. 1B. Bit lines and word lines run orthogonal to each other. In FIG. 2A is shown cross section of a twin MONOS array of prior art with bit diffusions BL0, BL1, BL2, and BL3, control gates CG0, CG1, CG2, and CG3, word line WL0 and nitride storage sites M0, M1, M2, M3, M4, M5, M6 and M7. Control gates, separate from the word lines lay above the nitride storage sites and the bit lines. FIG. 2B shows a schematic diagram of the twin MONOS array of prior art. In the conventional MONOS MOS transistor the programmable component under the control gate in the MONOS device is a nitride as shown in FIG. 2A. The twin MONOS memory unit is comprised of a control gate such as CG1 in CELLI[1] under which are two separate sites, such as M2 and M3, that are used as storage sites in composite nitride layers. The bit line diffusion, BL1, lies under the control gate, CG1, and an independent polysilicon word line, WL0, lies between the control gates of adjacent cells.
U.S. patent application Ser. No. 09/810,122, dated Mar. 19, 2001, is directed toward providing a twin MONOS memory cell organized in a metal bit array. In the metal bit twin MONOS array similar to that shown in FIG. 3 of the present invention, control gate lines run in parallel with the word lines in order to simplify the fabrication processing steps and masking levels. Thus the organization of the array must be arranged so that the metal bit lines run orthogonal to both the control gate lines and the word lines. The metal bit lines are connected by alternating contacts to the junction regions of the memory cells. The metal bit array is more similar to a folded bit line array. Control gate lines are parallel to and alternate with word lines. Due to the xe2x80x9cLxe2x80x9d shape of the memory cell, the bit line selection can not be independent of the control gate selection.
It is an objective of the present invention to provide a method of numbering and selection for the twin MONOS metal bit line memory array.
It is also an objective of the present invention to address a memory cell as a function of the word line, bit line and control gate of the twin MONOS metal bit line memory array.
It is yet an objective of the present invention to form a unique address that is a function of three dimensions of the twin MONOS metal bit line memory array.
It is another objective of the present invention to provide voltage conditions for the twin MONOS metal bit line array during a read operation.
It is yet another objective of the present invention to provide a method of voltage sensing while reading a cell of the twin MONOS metal bit line array.
It is still another objective of the present invention to provide a method of current sensing while reading a cell of the twin MONOS metal bit line array.
it is still yet another objective of the present invention to provide a method and voltages for a single cell erase operation.
A new method of selection and numbering for the metal bit memory array is introduced in the present invention. The address of a memory cell is the function of the word line, bit line and control gate. A unique set of address bits must incorporate all three dimensions in which the X dimension corresponds to the word line address, the Y dimension corresponds to the bit line address and the Z dimension corresponds to the control gate with an even and odd property.